PCB-level Jitter Sensitivity Measurement and Hierarchical PDN-Z based PSIJ Estimation for PCIe Gen5 SSD

In this paper, we first propose a methodology to predict Power Supply Noise Induced Jitter (PSIJ) by accurately measuring Jitter Sensitivity Function (JSF) and Power Supply Noise (PSN) at PCB-level and then converting them into on-chip level characteristics, respectively for PCIe (Peripheral Component Interconnect Express) Gen5 SSD host serial interface design. As a result, we successfully obtained on-chip level JSF and PSN from 1 MHz to 100 MHz which is a targeting frequency range to estimate PSIJ caused by off-chip noise sources in the SSD device.