Low Area Implementation of FIR Filter Based on FPGA Using Approximation Method

A new approach is proposed that synthesizes multiplier blocks with minimal hardware requirements than standard block FIR filters, making them appropriate for applications of FIR filters. The proposed method is done firstly by changing the structure of the FIR filter, then secondly by manipulating the coefficients of the FIR filter. This method is called the approximation method. A 16-order effective FIR filter is designed and implemented in this paper, Using the equiripple approach in MATLAB R2012a to create the FIR filter, which was subsequently realized on Spartan-3A xc3s700a-4fg484FPGA and simulated with Xilinx ISE (Integrated Software Environment). The proposed method achieved the lowest area minimization percentage among other techniques, which is as follows: There was a 79.69% decrease in the quantity of 4 input LUTs and a 68.07% decrease in the number of slices that were occupied. At the same time, the reduction in the min period is 79.49%.