Design and Implementation of Low Quantum Cost Reversible Universal Shift Register

This paper proposes a novel and efficient design of a 4-bit Reversible Universal Shift Register (RUSR) using reversible logic gates. RUSR performs shifting operations the same as CMOS-designed universal shift registers, such as left shift, right shift and parallel load, respectively. In this paper, we are designing a 4-Bit RUSR using a reversible Master-Slave D-Flipflop (RMSDFF) and reversible 4X1 Multiplexer (RMUX41). The proposed RMSDFF and RMUX41 are designed using Feynman (FG), Fredkin (F) and Modified Fredkin (MF) gates. Modified Fredkin gate plays a remarkable role in the implementation of the proposed optimized architecture. The efficiency of the proposed architecture is demonstrated in terms of garbage outputs (GO) and quantum cost (QC). The proposed architecture reduces the power consumption with a low quantum cost, a minimum number of reversible logic gates and garbage outputs. Due to this, the proposed design is particularly beneficial in quantum computing, Low-power CMOS design, and other applications. In this paper, the RUSR is designed by the proposed RMUX41 and RMSDFF, which are designed with the reversible logic gates using the hardware description language Verilog and verified with the simulated results using the ModelSim Altera tool.