Development of UVM Testbench for I3C protocol

The rapid evolution of semiconductor technologies and the increasing complexity of SoC’s have necessitated the use of robust and efficient design verification methodologies. Universal Verification Methodology (UVM),based on Systemverilog is a widely adopted standard for functional verification of the Register Transfer Level(RTL) design in the semiconductor industry.The Automotive,IoT and the Mobile SoC’s require many sensors to be integrated into the processor core.In this regard,the I3C (Improved Inter-Integrated Circuit) protocol developed by the MIPI Alliance,which combines the capabilities of SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Circuit), is gaining popularity in various applications due to its enhanced features and capabilities like increasing speed, reducing pin count.The main objective of this paper is to develop a reusable and efficient UVM testbench for verification of MIPI I3C-based designs.The development process entails creating a comprehensive UVM testbench with protocol-specific sequences, transactions, and coverage models tailored to the MIPI I3C protocol.