Design of DADDA Multiplier Using High Performance and Low Power Full Adder

The DADDA Multiplier circuit is an important component in digital Design. In mobile computing and digital signal processing (DSP), image and video processing applications it plays an important role. In this paper, a new and efficient approach of the DADDA multiplier circuit using high performance and low-power full adder is proposed. The proposed design utilizes a modified DADDA algorithm and employs a new architecture for the adder. The 32nm CMOS technology is used for designing the proposed DADDA multiplier circuit. The outcomes of the simulation demonstrate that the proposed circuit significantly improves both performance and power consumption. When contrasted to the conventional DADDA multiplier circuit, the proposed circuit can consume up to 57% less power while increasing speed by up to 32%.