Design and Verification of a High Frequency, SPI Control Block

This paper presents an improved digital serial peripheral interface (SPI) architecture containing five 8-bit registers. Eight parallel outputs are available among expected SPI pins, to make it suitable for serial to parallel data conversion. This peripheral is meant to operate at very high frequencies, over 55 MHz for different voltage supplies and across large temperature range. The robustness of this circuit is proved through digital functionality tests, IR-drop analysis, and defects simulations.