The Power Dissipation of Complementary Metal Oxide Semiconductor (CMOS) Inverter and Propagation Delay for Various Technologies

The primary goal of this research paper is to examine the impact of different design parameters on the power-delay product (PDP) in low-power very-large-scale integration (VLSI) circuit design. The focus is on analyzing the relationship between propagation delay (tp) and power consumption in these circuits. The effects of various factors, such as the widths of p-channel metal-oxide-semiconductor (pMOS) and n-channel metal-oxide-semiconductor (nMOS) transistors, load capacitance, and the supply voltage of the complementary metal-oxide-semiconductor (CMOS) inverter, are thoroughly investigated. To validate the findings, simulations are conducted using the personal simulation program with integrated circuit emphasis (P-SPICE) software. Additionally, a comparison is made between results obtained from different technologies (20 nm, 16 nm, 14 nm, and 10 nm) using values provided by the predictive technology model (PTM) for recent low-power applications (LSTP). This investigation aims to provide insights into the relationship between delay, power dissipation, and PDP in various technologies, assessing their suitability for low-power applications.