A simple approach to extract model for a floating-gate transistor

A new and simple approach to studying the model extraction is described in this work. This paper proposed the use of a standard industrial ICCAP tool in investigating DC model extraction for a floating-gate transistor which is well-known as the core element of many designs. The Level 3 model is deployed in modeling the transistor relying on the essential input requirements. The relations of drain current versus control gate voltage and drain voltage are presented with different geometries of width and length. The results proved excellent accuracy at large dimensions and promising at the smaller ones. In this work, the validation was conducted in the Cadence Virtuoso tool where the symbol, testbench circuits, and simulation conditions were defined. Furthermore, a comparative analysis is presented between the experimentally obtained data and the corresponding modeled outcomes, demonstrating favorable outcomes that validate the rigor of this study.