IC-Chip Behavioral Anomalies Experienced Under Intermittent Circumstances

Intermittent circumstances for an IC-Chip can be classified as Increased gate delays, Slow-to-rise/fall signals, Degraded signals, Increased RC delays, Increased leakage, Opens, Slow-to-rise signals, Slow-to-fall signals, Fails at high frequencies, Threshold voltage shifts, Weakened drive gates, Shorts, Defective interconnects, High/low Resistance interconnects, etc. Circuit configurations can significantly hinder or even block the diagnosis of these intermittent faults. Fault detection Interpretation for Intermittent failures in particular circuit configurations is limited, therefore IC-Chip Isolation and testing is necessary. This includes chip level pattern repetition, Frequency Span, Rise and Fall times settings, Hi and Lo and other test parameters settings. Hardware and Behavioral Modeling is a technique of using an actual chip to model its own behavior during simulation. Chip Output vectors are processed by the LASAR and Non-LASAR simulator. The Westest Hardware Modeler is a hardware modeler, an actual ATE, a chip behavioral modeler, a TPS integration ATE and has a IC-Chip intermittent fault detection mechanism. Utilizing the same setup as Unit-Under-Test pattern settings for IC-Chip test parameter testing and diagnosis can achieve an accurate diagnosis of an intermittent circumstance. Hardware and Behavioral Modeling is a simulation technique where the device or chip itself is used as the simulation model. An isolated IC-Chip can be setup not only to determine bad models and actual chip functionality but even to aid in chip diagnostics and intermittent failure detection. The detection method is setup by utilizing the actual ATE digital test unit and adjusting test parameters and test techniques as applied to the chip. In this case chip vectors and test parameters are sent to the chip by programming the digital test unit then appropriate test adjustments are made to determine if a chip fails intermittently. Intermittent Fault Detection for an individual IC-Chip is a hardware and software solution for testing and diagnosing intermittent faults where patterns are applied in a specific manner to detect intermittent faults; patterns can be adjusted for frequency, Rise and Fall, Hi and Lo, etc. This paper will show how an IC-Chip intermittent failure is detectable by isolating a chip. The paper will show how test parameters are adjusted and how results are interpreted. An actual sequence of events from ATE setup with digital test parameter adjustments on an isolated IC-Chip will show how an intermittent fault is detected.