Vertically Stacked Nanosheet Number Optimization Strategy for Complementary FET (CFET) Scaling Beyond 2 nm

Complementary field-effect transistor is considered to be one of the most promising structures to replace gate-all-around (GAA) field-effect transistors after 2 nm node and extend Moore’s Law. In this work, we develop the nanosheet (NS) count design strategy to address the mobility mismatch of electron and hole in standard complementary FET (CFET) cells, that is, nine-stage ring oscillator (RO), 6T-SRAM cell. The device characteristics are obtained by state-of-the-art physics-based TCAD simulations, and high-accuracy 3-D parasitic extraction is implemented in the device to circuit co-optimization flow. The simulation result of RO and SRAM circuits reveals that altering the ratio of nFET NSs (nNSs) and pFET NSs (pNSs) can match the mobility of electrons and holes, thus optimizing the performance and power of different circuits for different applications. For CFETs in nine-state RO cells, the CFET with four pNS channels and two nNS channels shows a 10% increase in frequency and 6% decrease in capacitance, but only a 3% increase in power consumption when compared to the CFET with three pNS channels and three nNS channels. Also take the “3 + 3” CFET as benchmark, for CFETs in SRAM cells, the “4 + 2” CFET delivers 10% extra static noise margin (SNM) and 8% ${I}_{\text {leak}}$ decrease, but the “1 + 2” CFET offers 12% extra SNM with 20% ${I}_{\text {leak}}$ increase, and advantage in terms of manufacturing process complexity.