Analyzing the Performance of 6T SRAM Cell and 64×64 Memory Array at Lower Technology Nodes for Low Power Design

SRAM plays an important role in achieving high computational speed in digital systems. Its fast access times, low latency, random access, and high reliability make it an essential component in modern digital systems. Due to its higher speed, it is commonly used in cash memory and realtime processing. However, as the size of the cache memory increases, the on-chip area requirement also increases. This can become a significant design challenge, especially for highperformance microprocessors and ASICs that require large amounts of cache memory. Thus, to address this challenge, designers need to optimize the size of the SRAM arrays used for cache memory while maintaining performance and stability. To meet all these requirements, designers have been focusing on the sub-micron level. So, this paper is dedicated to investigating the performance and stability of 6T SRAM cells in the deep sub-micron regime. It has been observed that the SRAM cell designed for the 22nm technology node has 92.0% less power dissipation, consumes 87.7% less area, and has 88.0% less delay in comparison to the 180nm node. Whereas the static noise margin (SNM) becomes worse at lower technology nodes. In addition, the stability of the SRAM cell has also been analyzed in terms of process corner analysis. The corner analysis reveals that the SF and FF are the best corners for optimum performance of the SRAM cell. We also realized the SRAM 64X64 (4Kb) memory array on 180nm and 45nm technology nodes. The memory arrays realized on 180nm consume 37.23 mW of power during read and write operations. Whereas the array designed on a 45nm technology node consumes 8.85 mW of power in read and write cycles, respectively.