3-D Stackable Offset-Via Antifuse by Cu BEOL Process in Advanced CMOS Technologies

The previous work proposed a 1-transistor-2-bit (1T2B) offset via antifuse memory implemented by FinFET CMOS logic processes. Through the self-aligned via process, spacing between via and metal can form a via-dielectric-metal structure, which can switch between states by forming a conductive path bridging the electrodes. In this 1T2B cell, multilevel cell (MLC) operation demonstrated by controlling the compliance current level enables higher storage density. The cell’s data reliability, stability, and disturbance have been evaluated through comprehensive tests. Among them, the issue of process variation has yet to be studied in detail. Therefore, this article will discuss this problem and propose a 1-transistor-1-bit (1T1B) structure solution that alleviates the possible misalignment problem in large-scale memory arrays.