A programmable image signal processing architecture for embedded vision systems

This paper presents a programmable multiprocessor architecture suitable for image preprocessing in embedded vision systems. The architecture is made up of sixteen 16-bit input/32-bit output parallel processing elements, connected to an intelligent DMA channel and frame buffers. Each element of the SIMD processing array can be programmed using a RISC-like instruction set, and is capable of performing DSP operations commonly used in image preprocessing algorithms. The architecture has been prototyped on an FPGA connected to a 256/spl times/256-pixel CMOS sensor, achieving 3.23 GOPS and up to 667 FPS of throughput at a clock frequency of 50 MHz. It is estimated to achieve a minimum of 6.46 GOPS and 1334 FPS at a clock frequency of 100 MHz when implemented in VLSI.