Research and Implementation of Multi-Core Stack Processor Based on AXI Bus

As the complexity of embedded systems continues to rise, enhancing the performance of stack processors and exploring the value of multi-core stack processors have become imperative. Building upon the research of a single-core stack processor model, this paper designs a multi-core stack processor model based on the AXI (Advanced eXtensible Interface) bus. Starting with the J1 single-core stack processor model, we introduce modules such as the AXI bus standard, finite state machine, and bus communication interface to construct a single-core stack processor model using the AXI bus. Taking this single-core model as the core, we achieve multi-core interconnection through shared bus communication. We design the Forth instruction system, memory units, and bus arbiter. Ultimately, a multi-core stack processor model based on the AXI bus is constructed. Prototypes of dual-core and quad-core multi-core stack processors are implemented on FPGA, both operating steadily at a frequency of 100MHz. Performance testing and validation are conducted on the Xilinx XC7A100T development board. The experiments demonstrate that the designed multi-core stack processor structure meets the design goals of high performance and low power consumption.