A 10-Bits 70-MS/s SAR ADC Based on Area-Efficient and Low- Energy Bootstrapped Switching Scheme using FIN-FET Technology

This paper primarily discusses two low-power design strategies for small area successive approximation registers (SAR) analog-to-digital converters (ADCs), both of which employ: The comparator is dual split switching, with a set and reset phase and a bootstrap switching technique. In this design, a SAR ADC is best suited for low power, medium resolution, and moderate speed applications. Based on a literature survey, low power consumption is attained by using Capacitive DAC by this average switching energy can be reduced significantly Capacitive DAC also incorporates a Time-and-Hold circuit in it. By using the FinFET CMoS technology in both switching schema and comparator in order to reduce power consumption. This had been designed and implemented using TSMC 18o-nm FinFET technology. The measurement results shown in the bootstrapped switching schema are by using the differential nonlinearity and integral nonlinearity of o.36 least significant bit (lbs.) and o.45 lbs., respectively. At a sampling rate of 7o-MS/s with a single 5-V threshold power supply, the power consumption was 3oo $\mu \mathrm{W}$. This design also achieved a signal-to-noise-and-distortion ratio of 79dB. The ADC design encrypted occupy an active area of 1o2 $\times 235\ \mu \mathrm{m}2$.