Design and Parametric Analysis of 6T SRAM Using 180nm and 45nm Technology

SRAM has high storage density and fast access time which made it a crucial component in many VLSI chips. Due to their simplicity of usage and minimal standby leakage, SRAMs are frequently utilized in mobile applications as both on-chip and off-chip memories. A CMOS SRAM cell uses less power and requires less read and write time. This study uses a 6T SRAM cell that consumes less power, space and time to read and write data. SRAM is a type of random-access memory, which stores data for longer duration without refreshing the circuits. This paper proposed to study the performance analysis of 6T SRAM in 45nm and 180nm technology in terms delay and average power using cadence tool. The aim is to develop a 6T SRAM design which yield less power and delay because most of the area on memory chip is consumed by SRAM cell. Transient analysis and DC analysis is carried out along with the waveforms which are simulated in GPDK 180nm and GPDK 45nm, comparison of various parameters along with the results have been depicted using cadence virtuoso.