Ultra Low Phase Noise VCXO with Crystal Filter Array

This paper demonstrates a 122.88 MHz VCXO module with ultra low phase noise within all frequency adjustment range for 5G infrastructure application. By applying a set of crystal array, the phase noise floor of one-cavity SMD-VCXO could be optimized from (-165) to (-170) dBc/Hz and the phase jitter of VCXO could be reduced from 45 fs to 25 fs . In comparison with TCXO of which output frequency has no significant deviation, the output frequency of VCXO has relatively large change due to its voltage control function. Thus, the central frequency and bandwidth of crystal filter become critical factors in this product. For the product architecture, the 122.88 MHz clock signal is generated from an one-cavity SMD-VCXO and this signal passes through a crystal filter array to improve the phase noise. The crystal filter array consists of at least two crystal resonators in parallel to widen the bandwidth of crystal filter. Finally, the signal would be transform into a specific squire waveform (CMOS, LVDS, LVPECL…) by a buffer amplifier. This technique provide a method to build a platform for optimizing the phase noise and miniaturizing the same grade product size.