Fast Frequency and Phase Tracking Analog PLL for Direct Carrier Synchronization

This article presents a wideband phase-locked loop (PLL) with a novel frequency acquisition loop for a wide locking range and wide bandwidth in 130 nm SiGe BiCMOS technology. The PLL contains two channels that work in parallel for the frequency acquisition and phase locking to form an analog phase frequency detector (PFD). The proposed frequency acquisition loop enables a fast frequency correction with a wide pull in range and accommodates frequency acquisition when a significant frequency difference is presented. The designed PLL provides the bandwidth of 55 MHz, a phase margin (PM) of 81.5°, and offers a wide frequency acquisition of 4.1 GHz. The proposed architecture allows simultaneous carrier synchronization and data de-modulations at front-end. The PLL has a measured phase noise of −124 dBc/Hz@1 MHz and the root mean square (rms) jitter integrated from 100 Hz to 1 GHz of 62.4 fs.