Power Loop Inductance Optimization Strategy for Eliminating Turn-off Switching Surge for GaN-HEMT Switching Device

The gallium nitride high electron mobility transistors (GaN-HEMTs) are increasingly applied for high-power switching converters. However, their fast switching in high-power applications tends to generate enormous switching surges at the turn-off, which may destroy the switching device. This problem can be mitigated by optimizing the wire structure to minimize the power loop inductance, although satisfactory reduction of this inductance is difficult in many practical designs. This paper address this issue by optimizing the power loop inductance rather than seeking the entire elimination of this inductance. This paper analytically elucidates the existence of the optimal power loop inductance that ideally generates no turn-off surge with fast-switching GaN-HEMTs. An experiment supported the analytical result, suggesting the optimal design of power loop inductance is promising for the power module design of GaN-HEMTs.