Design of Multi-Bit Full Adder Using Low Power m-GDI Technique

With recent advancements in VLSI circuits, adder circuits are constantly modified with different use of logic families such that power and area constraints are met. Full adder circuits have progressed from 28T to as low as 13T to satisfy the low-power technology nodes. This paper represents a novel approach to using twelve transistors to implement a full adder circuit. A hybrid technique of using transmission gate logic in combination with static complementary metal oxide semiconductors helps in accomplishing the functional and behavioral aspects of the circuit. The paper also examines the comparative analysis of traditional CMOS and TG logic full adder with the proposed hybrid-based full adder logic design. The analysis is based on the three input bits mainly 1, 4, and 8- bits respectively. Cadence virtuoso is used as the tool for the above study using GDPK 90nm technology. The parametric study helps in realizing the advantages of the circuit and the drawbacks to develop an enhanced full adder block.