An Approximate Full-Adder to Eliminate Carry Propagation in Lower Significant Stage of a Multi-Digit Adder

Approximate computing is prominently used in software and hardware design to optimize area, delay, and power consumption by exploiting the implicit tolerance for inaccuracy in applications. Adders are the vital building blocks of such error-tolerant and error-resilient applications. Though accurate adders give exact results, performance metrics like critical path delay, area overhead, and power consumed are improved in inaccurate adders. Motivated by this, we propose an approximate single digit full adder (AFA) using which addition of lower significant bits is implemented in an approximate multi-digit adder. The proposed multi-digit adder is a high-speed, area-efficient, and power-efficient architecture compared to the existing architectures. Computation accuracy in the least significant bits is sacrificed to improve the performance metrics of the adder. The trade-off between hardware cost and accuracy is also considered in proposed multi-digit inaccurate adder. Simulation results and mathematical model analysis show the advantage of proposed inaccurate multi-digit adder when compared to the existing architectures. Error analysis of the proposed inaccurate multi-digit adder proves that it is less prone to errors. Simulation results show that the image quality metrics like Mean Square Error (M.S.E), Peak Signal to Noise Ratio (PSNR), and Structural Similarity Index (SSIM) are also better for the proposed inaccurate multi-digit adder when compared to the existing architectures.