ATMR design by construction based on two-level ALS

The transistor scaling improved the integration of semiconductor devices but also made them more susceptible to faults. The triple modular redundancy (TMR) is a well-known logical masking technique that uses three copies of a given circuit and majority voters, which guarantees 100% in single fault coverage in the replicated modules at the cost of more than 200% in area overhead. The Approximate TMR (ATMR) concept exploits non-exact module functionality to reduce related area overhead at the cost of a reduction in fault coverage. An approximation cannot be made over more than one module to guarantee that the ATMR is logically equivalent to the original circuit. This work presents a novel ATMR design strategy based on two-level approximate logic synthesis that generates an effective by-construction ATMR. The proposed technique provides a flexible trade-off between area overhead and fault coverage during the ATMR building. Experimental results with combinational circuits have shown an average reduction in the TMR area overhead of 42% and 113% for a fault coverage greater than 99% and 91%, respectively.