Towards Low-Complexity, Fully Parallel and Flexible Hardware Realization of DCT/IDCT

The discrete cosine transform (DCT) and inverse DCT (IDCT) are crucial in various applications, such as image/video processing, data compression, and wireless communication systems. This brief presents a novel parallel, flexible, and low complexity hardware architecture for computing four common types of DCT and IDCT for signals with arbitrary lengths. The proposed scheme utilizes the processing-in-memory (PIM) technique as the computing paradigm to achieve fully parallel DCT/IDCT computations, enabling ultra-high throughput and low latency. To further enhance hardware efficiency and reduce hardware cost, an efficient coefficient mapping scheme is introduced, leveraging the symmetry properties of cosine function. Remarkably, the proposed scheme reduces the computational complexity by orders of magnitude compared to traditional DCT/IDCT implementations.