Thermal simulations of lock-in-thermography for failure analysis of integrated circuits

This paper describes a methodology that uses ANSYS workbench as a finite element (FE) simulator together with lock-in thermography (LIT) for accurately determining defects that are deeply buried and situated near the die edge of a stacked die device. The correlation provides a baseline for determining the critical defect location in cases where the hottest thermal site is detected outside of the silicon die region.