A Secure Design Methodology to Prevent Targeted Trojan Insertion during Fabrication

Hardware Trojans are malicious modifications made to a circuit for the purpose of altering its behavior. If Integrated Circuit (IC) fabrication is outsourced to an untrusted foundry, learning the correspondence between the layout and logical design nodes can enable that foundry to strategically choose target sites for adding Hardware Trojans to the layout. Split manufacturing mitigates this threat by printing only FEOL layers in the untrusted foundry, and then completing the design in a trusted facility. In this work we propose a new synthesis-based approach for k-secure personalization in split manufacturing.Based on the design, cell library, and user-specified security level k, our approach automatically chooses a subset of library cells for technology mapping, and then scalably partitions the mapped design to identify security-critical wires that must be withheld from the untrusted foundry. We demonstrate our approach by implementing four publicly available benchmark designs in a 15nm open cell library across a wide range of security levels from 10-100,000. We show that our method appropriately tailors library cell choices according to design and security level, and that the secure partitioning algorithm scales to thousands of cells and beyond. Designs created with our method achieve a high level of security even while withholding as little as 9% of wires from the untrusted foundry. Our method is furthermore able to explore tradeoffs by generating a set of equally-secure designs that are Pareto-optimal in area versus number of wires withheld.