Role of Cu/SiO2 Rough Interface in TSV for High-Power Device Under Electromigration

Through silicon via (TSV) technology is considered as the most promising 3-D packaging method due to its excellent electrical performance. However, the electromigration (EM) effect seriously reduces the reliability and service lifetime of TSV, which is conducive to the growth of holes and the uneven accumulation of Cu atoms in TSV-Cu and leads to short circuits of power devices. In addition, the roughness caused by the through-hole etching process accelerates the crack propagation at the Cu/SiO2 interface, resulting in local failure. In this work, a novel EM modeling approach for TSV with a rough interface using the W–M fractal function was reported. The mechanism of the EM effect of interface with different roughness was investigated. There is a significant concentration of current and stress under the increasing roughness, which intensify the atomic flow at the interface and result in the formation of a large number of voids and hills. Moreover, the increase in working current can also contribute to the obvious EM effect, and a larger current density will reduce the high-temperature reliability of TSV for high-power device.