How serious is the issue of backside Cu contamination in CMOS integrated circuits?

Experimental results are presented on the effects of intentional copper contamination on the performance of NMOS and PMOS devices in CMOS integrated circuits (ICs). Intentional copper contamination was introduced from the wafer backside using either PVD copper, or CuSO/sub 4/ electroplating solution or copper ion implantation. High temperature annealing was carried out to drive-in the copper species. Regardless of the method of intentional copper contamination, there was little or no change in the electrical parameters of both NMOS and PMOS devices. Secondary Ion Mass Spectroscopy (SIMS) analysis showed that very little copper diffused into silicon, leading to no device degradation.