10-bit 45.5Ms/s SAR ADC based on Multi-Segmentation Split-Capacitive DAC

This paper presents a 12-bit 45.5Ms/s SAR ADC in TSMC 0.18μm CMOS process. With the proposed architecture, a multi-segment split capacitor DAC was used to reduce the total capacitance and the possibility of capacitor switching. To reduce the swing range of the common voltage, hybrid capacitive switching was applied to the MSB and monotonic capacitive switching was applied to the LSB. In the CMOS process, split capacitors cannot achieve accurate fractional values. Therefore, non-fractional values are also used to solve the problem of capacitor mismatch. The final measurement data shows INL ranges around -0.71 to 0.64 and DNL ranges around -1.0 to 1.032. Total capacitance reduced by 75% relative to CDAC.