A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications

This article presents a four-phase time-based switched-capacitor low-dropout (SCLDO) regulator that regulates an output load voltage ( $V_{\text {OUT}}$ ) of 0.35–0.95 V with an input voltage ( $V_{\text {IN}}$ ) of 0.45–1 V. The regulator employs a four-phase time quantizer, which enables high proportional gain control and short transient response time with relatively low quiescent current. In addition, the proposed SCLDO employs a 9.6-pF coupling capacitor ( $C_{\text {C}}$ ) that is connected to the gate voltage of the pass transistor and $V_{\text {OUT}}$ node, thereby reducing the $V_{\text {OUT}}$ voltage drop during the load transition. Because the SCLDO utilizes capacitor components when charging and discharging $C_{\text {C}}$ , it provides robustness to process and temperature variations even at low- $V_{\text {IN}}$ conditions. Therefore, the proposed time-based SCLDO achieved a $V_{\text {OUT}}$ settling time of 4.4 ns at $V_{\text {IN}}$ = 1 V and 13 ns at $V_{\text {IN}}$ = 0.5 V condition. Fabricated in a 28-nm CMOS process, the proposed time-based SCLDO achieves a maximum $I_{\text {OUT}}$ of 400 mA and a figure of merit (FoM) of 3.0 fs, with an active area of 0.021 mm2.