Integrated Circuit Mask–Generative Adversarial Network for Circuit Annotation With Targeted Data Augmentation

In recent years, deep-learning-based segmentation techniques have been applied to circuit annotation for the hardware assurance of integrated circuits (ICs). However, imperfections in circuit images often cause incorrectly segmented pixels, which result in critical circuit connection errors that are detrimental to subsequent circuit analysis. To mitigate such circuit connection errors, this article proposes a targeted data augmentation framework for deep-learning-based circuit annotation, termed IC Mask–Generative Adversarial Network (ICMG), which generates circuit images containing the aforementioned imperfections through generative-adversarial-network-based image translation from synthetic circuit masks. The circuit masks are synthesized by a novel mask generation process that incorporates our domain knowledge of IC layouts and is configurable to emulate various image imperfections, such as material residuals in the sample preparation or distortion in the imaging process. In our experiments on a microcontroller IC, our proposed ICMG greatly reduced the circuit connection errors and the required manual effort for data labeling compared to the reported techniques.