An Improved Noise Canceling Sturdy 2-1 MASH Sigma-Delta Modulator with Multi-Bit SAR Quantizer

An improved delay-based noise canceling (DNC) sturdy 2-1 MASH Sigma-Delta modulator is designed in this paper, which eliminates the quantization noise of the first noise shaping loop compared with the traditional structure. SAR quantizer and data weighted average (DWA) are used to reduce the nonlinear problem of power consumption and feedback DAC. The circuit design uses $0.18\mu \mathrm{m}$ CMOS standard technology, the working power supply voltage is 3.3V, the sampling rate is 2.56MHz, the signal bandwidth is 20kHz, the peak SNDR is 102.2dB, the significant bit is 16.68bit and the overall power consumption is 2.87mW.