Study of Breakdown Voltage Improvement of High-Voltage PLDMOS

In this paper, the method of high-voltage PLDMOS breakdown voltage (BV) improving is studied, in which high-voltage NLDMOS BV is not sacrificed. The method is increasing high-voltage PLDMOS drift region dose of high energy implant and decreasing that of middle energy implant, but the PNP punch-through BV of high-voltage PLDMOS is suffered in this method. Then both BV and PNP punch-through BV are considered, finally, the high-voltage PLDMOS which both BV and PNP punch-through BV meet target is got in TCAD simulation.