Iterative and Verifiable Retiming for FPGA Performance Optimization

Reducing the critical path delay is the key to optimizing the circuit performance since it determines the maximum operating frequency. Retiming is a synchronous circuit transformation that can reduce the critical path delay by moving registers across combinational circuit elements. Compared with ASIC, more than 55% physical delays of FPGA come from the interconnection. Hence it is beneficial to use these interconnection delays for FPGA retiming. However, FPGA retiming is normally carried out before or during placement and routing without precise static timing analysis (STA), which leads to inaccurate physical timing optimization results. In addition, it is also a difficult task to verify the functional equivalence of circuits before and after retiming. In this paper, we propose an iterative and verifiable retiming algorithm, which extracts critical path information from the STA report and iteratively performs retiming by modifying BLIF netlist based on the physical interconnection delay, rather than the logic depth. Our experimental results based on VPR benchmark demonstrate that our method can reduce critical path delay by 5% on average while ensuring the functional equivalence. Compared to retiming in ABC, which lacks physical timing information, our method achieves smaller delay with fewer registers used. Compared to Vivado retiming gain on Virtex-7, the proposed method can achieve an 1.3% retiming gain improvement on k6_Frac_N10_Frac_Chain_Mem32K_40nm in VPR.