A Low Phase Noise Programmable Divider Operating at 24GHz in a 65-nm CMOS Technology

This paper presents a low-power, low-phase noise programmable divider in a 65nm CMOS technology. The division ratio can be varied between 256 and 8444, with a step size of 4. The divider consists of a prescaler, an 8/9 dual-mode divider, a programmable pulse-swallowing counter, and a carry module that allows the programmable swallow counter to carry to the programmable counter. In the case of operating voltage of 1.2V and input signal of 24GHz, the post layout simulation shows the phase noise can be as low as −150.5dBc/Hz at a frequency offset of 10kHz, with a power consumption of 20mW, and a layout area of 43. 2mm².