Fast Update Algorithm With Reorder Mechanism for SRAM-Based Longest Prefix Matching on FPGA

Longest prefix matching (LPM) is often used in network forwarding and it is usually implemented by ternary content addressable memory (TCAM) on field programmable gate array (FPGA). The traditional SRAM based TCAM only has one clock cycle in search delay, but it has a non-negligible update latency. Different from the general TCAM words, the ternary bits in LPM words are arranged continuously from low bits to high, and the prefix lengths of words have some distribution characteristics on actual network traffics. In this brief, a design is proposed to reduce the update latency of LPM by fast update algorithm with reorder mechanism. The key idea is reorder LPM prefix and partition don’t care bits into each sub-prefix evenly in SRAM based LPM, so that the update latency in each sub-table would be minimized and the whole update latency would be reduced. The design of this brief is implemented on Xilinx Kintex-7 field-programmable gate array. Compared to the prior methods, the update latency of LPM is reduced by at least half or more in most cases with our method. As far as we know, this is the fastest update mechanism in SRAM based LPM, which consumes the least possible clock cycles.