DC-bus Neutral Voltage Balancing Based on DΣ Control Method

This study proposes a half-bridge dc-bus spilt-capacitor voltage balancing circuit based on DΣ control. The circuit can be designed according to the load requirements and be connected to a three-phase four-wire inverter. The balancing circuit is used to eliminate dc offsets due to process errors in the upper and lower arm dc-bus capacitor voltages and to eliminate ac components due to unbalanced loads. In addition, this method incorporates the neutral current into the calculation, so that the capacitor voltages are effectively balanced regardless of the load phase or amplitude imbalance. Finally, a dynamic model of the voltage balancing system is derived and validated with Matlab / Simulink numerical analysis software.