An Instruction Extension Based SHA-3 Algorithm Co-Processor Design Scheme

Cryptography is the cornerstone of securing information, and the traditional way of deploying cryptographic algorithms has the problems of slow computation speed and low flexibility. In this paper, we first analyze the principle and computation process of SHA-3 hash algorithm, propose a cryptographic instruction extension method to solve the problems in the traditional cryptographic algorithm deployment method according to the characteristics of the hash algorithm, and develop a cryptographic instruction extension scheme combined with Hummingbird E203 processor, carry out the design of co-processor hardware unit, build a behavior-level simulation and FPGA board-level verification environment, and carry out The correctness of the coprocessor function is verified and the performance is analyzed and compared. The experimental results show that the designed cryptographic instruction scheme can reduce the number of instructions and cycles by more than 90% with less than 8% increase in hardware resources and 9mW power consumption, which achieves a more obvious performance improvement and is suitable for resource-constrained scenarios.