Multi-Stage Comparator Progressive Offset Cancellation f or SAR ADC

Low power consumption is a significant advantage of SAR ADCs, while comparator is the main power consumer. In this paper, a progressive calibration method for comparator is proposed, which allows the power consumption of SAR ADC to vary linearly with the sampling rate, and improves the conversion time utilization and SAR ADC speed through the progressive calibration. A 16 bit 1 MSPS SAR ADC with the proposed comparator was design in 0.18um CMOS process. The prototype achieves 93.6db SNDR at 20-kHz input while operating at 1 MS/s and comparator consumes 6.5mW. It was drown in 0.18um CMOS and occupies 0.82mm².