An Algorithmic State Machine Design Approach for Digital Divider Controller

The algorithmic state machine (ASM) is a method for describe the desired operation of the device and design the control logic based on the detailed ASM chart. Binary divider is one of the most important components in microprocessors and digital signal processing systems. Achieving efficient realization of the binary divider may have a significant impact on the specific applications in terms of speed, power dissipation and area. In this paper a binary unsigned divider presented. A shift-subtract binary divider is designed. The binary divider architectures are encoded in the very high hardware description language (VHDL) and synthesized with ALTERA QUARTUS II 11.0 software. In order to analyses the proposed binary divider performance, Register- Transfer Level (RTL) simulation has been carried out using the Model-Sim Altera 6.6 b. For the design approach, using 4-bit divisor, and 8-bit dividend a 386 MHz user clock has been achieved. The architecture utilizes 27 combinational ALUTs16 registers, and dissipates a 0.82mw.