Design and Implementation of 1KB SRAM array in 45 nm Technology for Low-Power Applications

Static Random Access Memory (SRAM) is a critical component of digital circuits as it is used for high-speed data storage and retrieval. The 6T SRAM cell is a popular type of SRAM cell, which is widely used in various electronic devices such as microprocessors, DSP, and FPGA applications. In this paper, we present a detailed analysis of the 6T SRAM cell. We discuss the working principle of the 6T SRAM cell, its design considerations, and performance analysis.The primary objective of the study is to develop a memory array that consumes minimal power, has low leakage, and is compact in size. The array has a 1024-bit capacity, and read and write operations’ power requirements have been extensively investigated. The power consumption during read and write operations of proposed 1KB SRAM array structure is 50.46 µW and 410 µW, respectively. The paper highlights the importance of power dissipation in CMOS-based SRAM arrays and compares the performance attributes of the proposed array with those of previous works. The operation of a 45 nm 6T SRAM memory cell was validated using the Cadence Virtuoso tool.