Implementation of a recursive segmented multiplier using Static Segmentation

Low power consumption is one of the most crucial aspects of Very Large Scale Integration (VLSI) circuit design. Approximate computing is a novel processing paradigm in low power VLSI architecture. Designing a roughly recursive segmented multiplier based on the idea of static segmentation is the main goal of this study. A recursive multiplier is a roughly built multiplier that was created expressly to try to use less power. In this study, a roughly 8*8 recursive multiplier architecture is proposed that produces a 16-bit output. A verilog code is suggested to accomplish this goal, and the Nexys 4 DDR (Artix 7) FPGA family and the Xilinx Vivado design environment were used to build the design. When power consumption must be decreased but precision is not the major concern, static segmentation is a concept that is applied. Additionally, this paper compares the power consumption of approximate recursive multipliers based on static segmentation (SSM) and non-recursive multipliers based on SSM in this work.