A Low-Voltage Submicrowatt, High-Speed CMOS Dynamic Comparator

We present an energy-efficient dynamic comparator that is suitable for low-voltage and high-speed applications. The preamplifier circuit prevents fully discharging the output nodes without utilizing an extra capacitor, which improves power consumption and operating speed compared to other solutions. The comparator is designed in a 65-nm CMOS technology at a power supply of1.2 V. The designed comparator operates at a frequency of 1.2 MHz, consumes 931.1 nW, and has a delay of 0.64 ns at $\Delta \mathrm{V}_{\mathrm{i}\mathrm{n}}$=1mV. To estimate the offset of the proposed circuit, Monte Carlo simulations were performed and resulted in a standard deviation of 1.54 mV and a mean of 1.06 mV.