TrueAdaptTM- AI Based Maskless Patterning to Compensate for Die-Shift in Fan-Out Wafer Level Packaging

TrueAdapt™ offers an attractive solution to fan-out-wafer-level-packaging (FOWLP) and fan-out-panel-level-packaging, which offers significant cost savings as compared to similar bridge connection technology or interposers. Due to die-placement error and shift during molding, die assemblies on FOWLP can have significant die-shift. Design rules must ensure the accommodation of die-shift and as a result fine-pitch patterning is limited. TrueAdapt™ aims to solve that by utilizing in-line characterization of the die shift, generation of a new layout using the measured offsets, and patterning with direct-write lithography for high throughput wafer-level and panel-level fabrication at fine-pitches. In this work we present the fabrication of an assembly of dies interconnected in a daisy chain network with 10 µm pitch wiring on the FlexTrate™, a bio-compatible polydimethylsiloxane (PDMS) based FOWLP architecture. We measure die shift using optical metrology techniques to generate a stitched image of the assembly. The image is then processed using artificial intelligence (AI) computer vision to identify critical features on the dies (which are used to generate die-offsets for each die). Furthermore, we generate a layout based on measured die-shift that adaptively routes the wiring in between dies. Via and metal layers are subsequently patterned using direct-write lithography using a 405 nm lase. Direct-write lithography enables fine-pitch patterning at the wafer/panel level without the need for mask fabrication, promising significant cost savings. We further demonstrate a novel exposure technique based on focal extension that can be utilized to pattern over 100 µm of topography, making this a truly adaptive patterning process.