0.5 ¼m Pitch Wafer-to-wafer Hybrid Bonding with SiCN Bonding Interface for Advanced Memory

Heterogenous integration has become a sought-after solution for the semiconductor industry to achieve the system level PPACt™ (chip Performance, Power, Area, Cost and time to market) advancement. Wafer-to-Wafer hybrid bonding allows one to achieve high vertical interconnect density, enabled by small bond pad CD, tight pitch, and high percentage of Cu areal density. This paper showcases a robust integration flow for a wafer-to-wafer hybrid bonding with SiCN interface at 0.5 $\mu\mathrm{m}$ pitch. A six-level test vehicle was designed, unit processes were developed, and an integrated run-path was established for via-to-via bonding targeting advanced memory applications. This test vehicle has structures with DOE in bonding pitch $(0.5\ -1.2\mu \mathrm{m})$, bonding via CD (200 - 600 nm), and Cu areal density (4 - 25^%), in order to study the impact of each factor on bond quality. We have previously studied wafer-to-wafer hybrid bonding with a hermetic TEOS as the bonding layer. To address semiconductor fabs' roadmaps, this work focuses on using SiCN film as the bonding layers. SiCN films with varying compositions were screened for high bonding energy (>hermetic TEOS) at post-bonding anneal temperatures ranging from 200 - 350°C. Unit process for lithography, etch, CMP of Cu/SiCN, edge trim, top wafer grind and CMP of Si were developed. Metrology and inspection control points were established. The Cu/SiCN surface topography control by CMP is the most crucial factor to ensure good bonding. Repeatable CMP processes with precise and tunable Cu dishing profile is critical, especially for sub $-\mu \mathrm{m}$ tight pitches. A CMP process was established on Applied Materials' Reflexion LK Prime™, with a smooth SiCN surface finish (< 2 A RMS roughness) and desired Cu recess profile (< 2 nm dishing and < 1 nm variation). With this integration flow, partnering with EV Group, we demonstrated 0.5 $\mu \mathrm{m}$ tight pitch bonding across various test patterns on 300mm wafers.