A Method to Improve 3D Interconnections Resource Utilization and Reliability in Hybrid Bonding Process Considering the Effects on Signal Integrity

Hybrid Bonding (HB) process has gradually become the primary choice of advanced packaging in processor-memory heterogeneous stacking scenarios with its huge advantages of high interconnection density and low power consumption. However, enormous disparity between the bandwidth upper bound of advanced processors and the extremely high interconnection density of HB results in low interconnection resource usage and low robustness. In this paper, we propose a 3D interconnect design method “Multi-Bond Attach” (MBA) to improve the bonding resources utilization and reliability during chip stacking. To demonstrate the feasibility of the MBA approach and investigate the optimal number of bonding attach $(\mathbf{N}_{\mathbf{MBA}})$, it is essential to analyze the impact on signal integrity considering signal routing factors. We first investigate bond-to-bond coupling influence to construct rational models used for frequency/time-domain analysis and verify the correctness of the model construction procedure. After that, 4 MBA transmission models corresponding to 4 $\mathbf{N}_{\mathbf{MBA}}$ are constructed, and the signal integrity of the interconnect structures for different transmission cases is compared from the insertion loss and crosstalk in the frequency-domain and the eye height and timing jitter in the time-domain. Based on our results, we provide a design guidance for 3D processor-memory stacking designers regarding the interconnection scenario in the HB process.