Residual stress measurement of build-up layer in silicon wafers

Residual stress has been a big concern during the fabrication and assembly which may damage the electronic device or shorten the device's lifetime. Several methods have been developed to estimate residual stresses and are well-established. However, most of them have high costs or some limitations for the build-up material. A novel method is proposed in this study to analyze the residual stress induced in the build-up layer during fabrication and predict chip thermos-mechanical behavior with various sizes. Chips were first ground to different thickness and the warpage of different thickness chips at various temperatures was measured using Takaoka. A finite element analysis model was built. The residual stress can be obtained by correlating the warpage with experimental results and the effective modulus and thermal expansion coefficient of the build-up layer will also be carried out. This study provides insights into the commonly classified build-up layer information. This study can contribute to a better understanding of build-up layer information that is typically classified.