Design and Analysis of CNTFET based Dynamic Comparator

Comparators are an essential design module and component in modern digital circuits, digital signal processors, and data processing application-specific integrated circuits. Comparison is the most fundamental arithmetic operation since it establishes whether one number is higher than, equal to, or lower than another. The ubiquitous use of comparators in high-performance systems makes it highly necessary to find ways to reduce both their performance and their power consumption, despite the fact that the design of comparator logic is rather straightforward. As a result, a comparator that is both more rapid and more efficient in its use of energy is chosen. This work entails the creation of two distinct comparators, one with a static style and the other with a dynamic style, and it applies to both complementary metal oxide semiconductor (CMOS) technology and carbon nanotube field effect transistor (CNTFET) technology. This work utilizes the pass transistor logic (PTL) design strategy for developing the 2-bit magnitude comparator. The design approach that was just dissected gives a high degree of performance since it was constructed with the aim of achieving that level of performance in mind. The effectiveness of these two separate comparators inside their respective alternative design strategies was evaluated using the transistor count, power consumption, and delay, which are three crucial factors to take into account when building any digital circuit. Both of these comparators were found to have excellent performance. When constructing any digital circuit, it is important to pay attention to all three of these factors. Using the Synopsys HSPICE tool and 32nm technology, an analysis of the performance of the circuits is carried out.