A VLSI Architecture for the Node of Wireless Image Sensor Network

This paper proposes a novel design of VLSI architecture for the node of wireless image sensor network. This architecture aims at the SoC (System on a chip) implementation and is composed of a general purpose embedded processor and several dedicated hardware accelerators for image processing and wireless communication. The hardware implemented Image processing unit (IPU) adopts an innovative image processing approach which concludes Bayer Color filter array (CFA) pre-processing and lossless JPEG compressing. The IPU can process 5 frames/s (VGA full color resolution) under a 16 MHz system clock, reaching a 2.6~4.7 bits/pixel compression rate with the PSNR larger than 46.3dB. The hardware implemented Wireless communication unit (WCU) executes computing intensive and timing critical tasks of the IEEE 802.15.4 Media access control (MAC) layer, which can achieve high performance and low power consumption on wireless operations compared of software implementation. Furthermore, low power design and techniques are employed to extend battery life, resulting in 45mW maximum system power consumption when the system is in the full working mode (i.e. processor, IPU and WCU are active simultaneously). The proposed architecture has been proto-typed on an FPGA system and fabricated in 0.18µm CMOS process.