Energy Efficient Ternary Device in 28-nm CMOS Technology with Excellent Short-Channel Effect Immunity and Variation Tolerance Characteristics

Since the semiconductor industry has entered the hyper-scaling era, which requires a technology to itself appropriately to meet the demands of data-intensive computing, binary Boltzmann transistor is facing the integration density limits [1]. One efficient approach to overcome this challenge is the ternary system, where system complexity can be reduced to 63.1% of binary one [2]. Recently, various research efforts of ternary devices have been proposed [3]–[5]. However, these studies have not verified its ternary function under wafer-scale measurements yet. We have reported a wafer-level integrated and power-scalable ternary device technology (T-CMOS) [6]. In this work, we demonstrate a short-channel effect immune and variation tolerant ternary device using 28-nm CMOS foundry.