A theta (log n) algorithm for modulo multiplication

A theta (log n) algorithm for large moduli multiplication for residue-number-system (RNS)-based architectures is proposed. The modulo multiplier is much faster than previously proposed multipliers, and more area efficient. The implementation of the multiplier is modular and is based on simple cells, which leads to efficient VLSI realization. A VLSI implementation using 3- mu m CMOS process shows that a pipelined n-bit modulo multiplication scheme can operate with a throughput of 30M operations/s.<>